As shown in FIG. 1, current CMOS image sensors comprise an array 100 of pixel sensor cells, four (4) of which labeled 100a, . . . , 110d are depicted in FIG. 1. Each of the cells 110a, . . . , 110d are used to collect light energy and convert it into readable electrical signals. Each pixel sensor cell 110 comprises a photosensitive element, such as a photodiode, photogate, or photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in an underlying portion thereof. The group of four pixel cells 110a, . . . , 110d depicted in FIG. 1 include photosensitive element such as collection well or photodiode device structures 120a, . . . , 120d, respectively. A read-out circuit is connected to each pixel cell and often includes a diffusion region for receiving charge from the photosensitive element, when read-out. Typically, this is accomplished with a transistor device having a gate electrically connected to a floating diffusion region. The group of four pixel cells 110a, . . . , 110d depicted in FIG. 1 include polysilicon transfer gate structures 125a, . . . , 125d, respectively, for transferring charge from the respective photosensitive elements 120a, . . . , 120d across a surface channel to respective floating diffusion regions 130a, . . . , 130d, that include one or more transistors, e.g., CMOS FET devices having narrow FET gate regions 140, for selecting and gating a pixel output signal or, resetting the floating diffusion region to a predetermined charge level prior to charge transfer.
FIG. 2 depicts in greater detail a typical pixel sensor cell 110 taken along line A-A of FIG. 1. As shown in FIG. 2, image sensor cell 110 includes a pinned photodiode 20 having a pinning layer 18 doped p+ -type and, an underlying lightly doped n-type region 17. Typically, the pinned diode 20 is formed on top of a p-type substrate 15 or a p-type epitaxial layer or p-well surface layer having a lower p-type concentration than the diode pinning layer 18. As known, the surface pinning layer 18 is in electrical contact with the substrate 15 (or p-type epitaxial layer or p-well surface layer). The photodiode 20 thus has two p-type regions 18 and 15 having a same potential so that the n-type doped region 17 is fully depleted at a pinning voltage (Vp). That is, the surface pinning layer 18 is in electrical contact to the substrate in order to cut down on dark current. The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value, Vp, when the photodiode is fully depleted.
As further shown in FIG. 2, the n-type doped region 17 and p+ region 18 of the photodiode 20 are spaced between an isolation structure, e.g., a shallow trench isolation (STI) structure 40, and a charge transfer transistor gate 25 which is surrounded by thin spacer structures 23a,b. The STI region 40 is located proximate the pixel imager cell for isolating the cell from an adjacent pixel cell. In operation, light coming from the pixel is focused onto the photodiode where electrons collect at the n-type region 17. When the transfer gate 25 is operated, i.e., turned on by applying a voltage to the transfer gate 70 comprising, for example, an n-type doped polysilicon layer 70, the photo-generated charge 24 is transferred from the charge accumulating doped n-type doped region 17 via a transfer device surface channel 16 to a floating diffusion region 30, e.g., doped n+ type.
As mentioned, in each pixel image cell, the surface pinning layer 18 is in electrical contact to the substrate 15 of the same conductivity type. Currently, the surface pinning layer (e.g., p-type doped) of the pixel sensor collection diode is connected to the substrate via a well implant structure 150 (e.g., doped p-type) located on one of the edges of the collection diode 20. In practice, the underlying substrate well structure (e.g., p-well 150) is created by a mask implant technique, as are the photodiode and pinning layer structures and each are formed in separate processing steps.
It is also advantageous to have doping on the STI sidewall adjacent to the collection diode in order to minimize the dark current of the image sensor. If the n-type collection diode comes into contact with the STI sidewall, than any surface states along the silicon—STI interface will be uncovered by depleted silicon when the diode is in its reset state. This is the optimal condition for surface generation which would contribute to imager dark current. If the STI sidewall adjacent to the collection diode is doped p-type, holes will shield the surface and prevent generation.
One technique is to provide the adjacent isolation structure with a sidewall implant region for ensuring improved alignment of conductive material and proper electrical contact between the surface pinning layer above the collection well device and the underlying substrate.
Angled implant techniques for doping the STI sidewalls and bottom for providing electrical connection from the substrate to a surface pinning layer for the pixel imager cell to cut down on dark current are known in the art, for example, as described in United States Patent Application Publication No. 2004/0178430. A further method to allow the masking of such an angled implant with tight layout rules by rounding the corner of the photo resist is described in above-mentioned, commonly-owned, co-pending U.S. patent application Ser. No. 10/905,043.
While doping the sidewall of STI is useful in a pixel sensor on the portion of the STI surrounding the photo diode, it may have deleterious effects in other portions of the array. This is because higher doping on the STI sidewalls of narrow field effect transistors (FETs) can significantly increase the threshold voltage, decrease the drive current strength, and increase the substrate voltage sensitivity of the transistors. Furthermore, doping of the sidewall of a diffusion will partially counter dope the source-drain diffusions of those transistors. If the net doping result is low enough, this can cause generation current. All of these effects are counter to what is desired in an imaging cell. Thus, when the angled implant technique described in the prior art results in doping of the sidewall proximate the narrow FET gates 140, this leads to a totally unacceptable condition, especially as only narrow FETs are implemented in an image sensor where size is at a premium.
It would thus be highly desirable to provide an isolation structure used in isolating pixel sensor devices that include sidewalls that are selectively doped in order to avoid the disadvantageous effects that may result when implementing prior art techniques that may cause implant doping of isolation structure sidewall regions proximate to FETs.